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| CAT24C02C 2K-Bit Serial E2PROM FEATURES s 400 KHZ I C Bus Compatible* s 1.8 to 6.0Volt Operation s Low Power CMOS Technology 2 s Page Write Buffer s Self-Timed Write Cycle with Auto-Clear s 1,000,000 Program/Erase Cycles s 100 Year Data Retention DESCRIPTION The CAT24C02C is a 2K-bit Serial CMOS E2PROM internally organized as 256 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The the CAT24C02C features a 16-byte page write buffer. The device operates via the I2C bus serial interface and has a ISO 7816 compatible pinout. DIE PAD CONFIGURATION VSS DC DC DC BLOCK DIAGRAM VCC EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS SDA START/STOP LOGIC XDEC CONTROL LOGIC E2PROM SDA NC NC SCL DATA IN STORAGE PIN FUNCTIONS Pin Name NC SDA SCL VCC VSS DC Function No Connect Serial Data/Address Serial Clock +1.8V to +6.0V Power Supply Ground Don't Connect SCL STATE COUNTERS SLAVE ADDRESS COMPARATORS HIGH VOLTAGE/ TIMING CONTROL * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. (c) 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25086 -00 8/99 S-1 CAT24C02C ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to VSS(1) ................. -2.0V to +VCC + 2.0V VCC with Respect to VSS ................................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR (3) *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 VZAP(3) ILTH(3)(4) D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC ISB (5) Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V) Min. Typ. Max. 3 0 10 10 Units mA A A A V V V V Test Conditions fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC ILI ILO VIL VIH VOL1 VOL2 -1 VCC x 0.7 VCC x 0.3 VCC + 0.5 0.4 0.5 IOL = 3 mA IOL = 1.5 mA CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Test Input/Output Capacitance (SDA) Input Capacitance (SCL) Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Standby Current (ISB) = 0A (<900nA). Doc. No. 25086-00 8/99 S-1 2 CAT24C02C A.C. CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.8V, 2.5V Min. FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF (1) 4.5V-5.5V Min. Max. 400 200 1 1.2 0.6 1.2 0.6 0.6 0 50 Units kHz ns s s s s s s ns ns 0.3 300 0.6 100 s ns s ns Max. 100 200 3.5 Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50 1 300 tSU:STO tDH Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min. Typ. Max 10 Units ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 3 Doc. No. 25086-00 8/99 S-1 CAT24C02C FUNCTIONAL DESCRIPTION The CAT24C02C supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C02C operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. SDA: Serial Data/Address The CAT24C02C bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. I2C BUS PROTOCOL The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. PIN DESCRIPTIONS SCL: Serial Clock The CAT24C02C serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. Figure 1. Bus Timing tF tLOW SCL tSU:STA tHD:STA tHD:DAT tHIGH tLOW tR tSU:DAT tSU:STO SDA IN tAA SDA OUT 5020 FHD F03 tDH tBUF Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS 5020 FHD F04 Figure 3. Start/Stop Timing SDA SCL 5020 FHD F05 START BIT Doc. No. 25086-00 8/99 S-1 STOP BIT 4 CAT24C02C START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C02C monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. The CAT24C02C responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When the CAT24C02C is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24C02C will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24C02C (see Fig. 5). The next three significant bits are all zeros. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24C02C monitors the bus and responds with an acknowledge (on the SDA line). The CAT24C02C then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C02C. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24C02C acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24C02C writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as counter will `wrap around' to address 0 and continue to Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 5020 FHD F06 5 Doc. No. 25086-00 8/99 S-1 CAT24C02C Figure 5. Slave Address Bits 24C02C 1 0 1 0 0 0 0 R/W the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT24C02C will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten. Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24C02C in a single write cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT24C02C initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C02C is still busy with the write operation, no ACK will be returned. If the CAT24C02C has completed the write operation, an ACK will be returned and the host can then proceed with thenext read or write operation. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C02C acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24C02C then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the immediate Address READ or Selective READ operations. After the 24C02C sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C02C will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24C02C is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24C02C address bits so that the entire memory array can be read during one operation. If more than 255 bytes are read out, the counter will "wrap around" and continue to clock out data bytes. READ OPERATIONS The READ operation for the CAT24C02C is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24C02C's address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E = 255 for 24WC02), then the clock out data. After the CAT24C02C receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Doc. No. 25086-00 8/99 S-1 6 CAT24C02C Figure 6. Byte Write Timing S T A R T S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS DATA S T O P P 5020 FHD F08 Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE ADDRESS * A C K BYTE ADDRESS (n) DATA n DATA n+1 DATA n+P S T O P P A C K A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Figure 8. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE ADDRESS S T O P P A C K DATA N O A C K SCL 8 9 SDA 8TH BIT DATA OUT NO ACK STOP 5020 FHD F10 7 Doc. No. 25086-00 8/99 S-1 CAT24C02C Figure 9. Selective Read Timing S T A R T S A C K S T A R T S A C K A C K DATA n N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS * BYTE ADDRESS (n) SLAVE ADDRESS Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x S T O P P 5020 FHD F12 ORDERING INFORMATION Prefix CAT Device # 24C02C Suffix W I -1.8 Optional Company ID Product Number 24C02C: 2K Temperature Range Blank = Commercial (0 - 70C) I = Industrial (-40 - 85C) A = Automotive (-40 - 105C)* Package W: Wafer Form Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V Doc. No. 25086-00 8/99 S-1 8 CAT24C02C This Page Intentionally Left Blank 9 Doc. No. 25086-00 8/99 S-1 |
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